Performance and programmability comparison of the thick control flow architecture and current multicore processors

Abstract Commercial multicore central processing units (CPU) integrate a number of processor cores on single chip to support parallel execution computational tasks. Multicore CPUs can possibly improve performance over for independent tasks nearly linearly as long sufficient bandwidth is available. Ideal speedup is, however, difficult achieve when dense intercommunication between the or complex memory access patterns required. This caused by expensive synchronization and thread switching, insufficient latency toleration. These facts guide programmers away from straight-forward toward error-prone programming techniques. To address these problems, we have introduced Thick control flow (TCF) Processor Architecture. TCF an abstraction computation that combines self-similar threads into entities. In this paper, compare programmability entry-level two Intel Skylake commonly used kernels find out how well our architecture solves issues greatly reduce productivity software development. Code examples are given experiences recorded.